1. Field of Invention
The present invention relates generally to a flip chip interconnected structure and a fabrication method thereof. More particularly, the present invention relates to an improved flip chip interconnected structure having good electrical connection and a fabrication method thereof.
2. Description of the Related Art
With the increasing need for high-density devices for use in lightweight, portable electronics, there has been a gradual shift in sizes of integrated circuits and their package configurations. This gradual shift has resulted in developing various techniques for different package types.
A flip chip interconnected technology utilizes solder bumps on bonding pads of a chip to electrically connect to a substrate. Comparing the flip chip interconnected method to a wire bonding method and a tape automatic bonding method, the circular path of the flip chip interconnected package is shorter and the electrical properties are better. The bumps are arranged in a matrix shape; thus, the amount of pin outs of the chip is significantly increased. Since the flip chip technique is faster, denser, thinner, lighter and provides a low cost package, one can expect the flip chip technique to replace wire bonding.
FIGS. 1 and 2 illustrate schematic views of a conventional flip chip package. Referring to FIG. 1, a chip 110 has an active surface 112, and a plurality of bonding pads 114 are arranged on the active surface 112. A plurality of bumps 116 are formed on the bonding pads 114 of the chip 110. A substrate 120 has a surface 122, and a plurality of nodes 124 are formed on the surface 122. A position of each node 124 corresponds to a position of each bump 116. A stencil printing process is carried out to apply solder paste onto the substrate 120. A plurality of solder structures 130 are formed on the nodes 124 of the substrate 120. Referring to FIGS. 1 and 2, a bonding process is performed to bond the chip 110 to the substrate 120. The bumps 116 of the chip 110 are bonded to the solder structures 130 of the substrate 120 in a reflow oven. A reflow method allows the bumps 116 to combine with the solder structures 130 to form a plurality of solder balls 140. The chip 110 is electrically connected to the substrate 120 by the solder balls 140.
Referring to FIG. 2, a filling process is carried out to fill a gap between the chip 110 and the substrate 120 with a molding compound 150, and the molding compound 150 encapsulates the solder balls 140.
However, in the reflow process, the substrate 120 will bend due to the heating in the reflow process. The distance between the chip 110 and the substrate 120 at a center region is closer due to the bending effect, and the distance between the chip 110 and the substrate 120 at the end regions is greater. Stress caused by the bending effect can affect the bonding between the chip 110 and the substrate 120. The solder balls 140 will easily detach from the nodes 124, and the stress due to the bending can also affect the reliability of the device. Thus the electrical connection and the reliability of the product are affected.
A conventional method utilizes a clamp (not shown) to hold the chip 110 and pre-heat the chip 110 for a while during a bonding process. Once the heat is transferred to the bumps 116, the bumps 116 will combine with the solder structures 130 to form the solder balls 140. Thus the chip 110 is electrically connected to the substrate 120. Although this method can prevent the substrate from bending, the pre-heating process on the chip 110 can damage the chip 110 because the chip is pre-heated for about 20 to 30 seconds at a temperature of about 200xc2x0. The conventional method complicates the fabrication process and the quality of the product is not reliable.
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, the present invention provides a flip chip interconnected structure comprising a substrate having a surface, a chip locating region and a plurality of nodes. The chip locating region is on the surface of the substrate and the nodes are formed on the chip locating region. A chip is provided and has an active surface, on which a plurality of bonding pads are formed. The active surface of the chip corresponds to the surface of the substrate. A plurality of solder balls are respectively connected to the bonding pads and the nodes, wherein sizes of the solder balls are varied to allow the chip to bond to the chip locating region of the substrate. A molding compound is filled in between the chip and the substrate and is used to encapsulate the solder balls. The solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region.
It is another object of the present invention to provide a flip chip interconnected structure comprising a chip that has an active surface on which a plurality of bonding pads are formed. A substrate also is provided and has a surface, a chip locating region and a plurality of nodes. The chip locating region is on the surface of the substrate and the nodes are formed on the chip locating region. The chip locating region further comprises solder mask openings, and the nodes are exposed by the solder mask openings. Sizes of the solder mask openings are varied. A plurality of solder balls are respectively connected to the bonding pads and the nodes. The chip is bonded to the chip locating region of the substrate by the solder balls. The active surface of the chip corresponds to the surface of the substrate. A molding compound is filled in between the chip and the substrate and is used to encapsulate the solder balls. The solder mask openings are arranged in a matrix, and sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.
It is another object of the present invention to provide a method of fabricating a flip chip interconnected structure. The steps of the method comprise first providing a chip that has an active surface. A plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads. A substrate is provided, which has a surface and a chip locating region. The chip locating region is on the surface of the substrate, and a plurality of nodes are formed on the chip locating region. Solder paste is used to cover the chip locating region and the nodes. The solder paste forms a plurality of solder structures with various sizes. A bonding process is performed to bond the active surface of the chip to the surface of the substrate by bonding the bumps to the solder structures. A heating process is carried out to combine the bumps and solder structures to form a plurality of solder balls. The solder balls are bonded respectively to the bonding pads and the nodes. The chip is bonded to the chip locating region of the substrate through the solder balls. A stencil printing board has a plurality of openings. The stencil printing board is located on the substrate and the nodes are exposed by the openings. The openings are filled with the solder paste by a screen printing method. Positions of the solder paste correspond to positions of the nodes. The solder paste forms solder structures with various sizes because the sizes of the openings are different. The openings are arranged in a matrix, and sizes of the openings located at a peripheral region of the stencil printing board are larger than sizes of the openings near a center region of the stencil printing board. Therefore, the amount of solder paste filled in the opening at the peripheral region is more than the amount of solder paste filled in the openings at the center region.
It is another object of the present invention to provide a method of fabricating a flip chip interconnected structure. The steps of the method comprise first providing a chip having an active surface. A plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads. A substrate having a surface is provided, wherein a chip locating region is on the surface. A solder mask layer and a plurality of nodes are formed on the chip locating region. A plurality of solder mask openings are formed on the solder mask layer, and the nodes are exposed by the solder mask openings, wherein the solder mask openings have various sizes. Solder paste is used to cover the chip locating region and the nodes. A bonding process is performed to bond the active surface of the chip to the surface of the substrate by bonding the bumps to the solder paste. A heating process is carried out to combine the bumps and solder paste to form a plurality of solder balls. The solder balls are bonded respectively to the bonding pads and the nodes. The chip is bonded to the chip locating region of the substrate through the solder balls. Sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.